Re: [f-cpu] Re: Floating-Point

[Michael Riepe <michael@stud.uni-hannover.de>]

On Tue, Aug 21, 2001 at 10:18:45AM +0200, Yann Guidon wrote:
[...]
> > > > Something is missing: the lines that select the instruction to execute
> > > > (if the unit can handle more than one instruction).
> > > ??
> > Signals like Sub/Saturate in the ASU, or MacH/MacL in the IMU.
> in the ROP2 unit, these are "mode" flags and "function" flags, right ?
> add/substract would be a "function" and "saturation" would be a "mode"
> flag, i guess.

That's it, exactly.

> The Fetcher and the decoder have to "hold" some instructions,
> when a certain signal is asserted. by default, i use a MUX
> that loops the output to the input, under the control of the
> "next instruction" signal. However, the clocking is often not
> defined _inside_ the units but at the top level of the design.
> One year ago (approximately) we have tried to define a "generic"
> Flip-Flop gate but it is not satisfying yet.
> Could you (nicO and Michael) try to make this kind of generic gate ?

You mean, like this?

	process (Clk)
	begin
		if rising_edge(Clk) then
			if to_X01(Enable) = '0' then
				Output <= Input;
			end if;
		end if;
	end process;

Synopsys can turn that into a clock gate if you tell it to do so.
I've been using it in the latest versions of the multiplier, too.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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