Re: [Fwd: [f-cpu] the wrong way (of floating point and so on)]

[Kim Enkovaara <kenkovaa@cc.hut.fi>]

On Mon, 27 Aug 2001, Ben Franchuk wrote:

> How high level will the tools be? A adder could be a stock adder
> or custom designed
> one at the transistor level? Ripple carry? Carry lookahead?
> Carry-skip?

I think in the beginning F-CPU should use the adders the synthesizers
produce. They are so much faster to produce (I mean writing + sign is
faster than creating adder with complex generate structures :)). There is
time after the functional testing and proof on concept to tinker with the
small bits and optimize the design. Even if the design runs at 1 MHz
without optimization that is way faster for testing than simulation.

> > OTOH according to some figures given by nicolas, a FC0 ASIC could
> > reach 400MHz in .18u.
> 
> Did you know intel is claming a 2 GHZ chip? Still 400 MHZ is not
> to shabby.

Intel has very long pipeline in the chip which helps in the MHz rally.
Intel also knows their ASIC process very well, each chip is tailor made
for the process. I bet they have tools to use all their different cells at
the same time (low power/slow, power hungry/fast etc.) Many ASIC vendors
support only one library at the same time currently, but this is changing
with the new design flows.

And full custom design can do wonders sometimes, but it takes huge amounts
of time and ties you to one process.

=============================================================================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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