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Re: [f-cpu] the wrong way (or not?)



> > i think that some people here have some means.
> > however, without complete source code, it's almost
> > useless :-(
> 
> Anybody out there? By the way, what is still missing?
> 
> JG

Are the DOC's current? If you have the DOC's you can then
generate the logic design, but not the other way around.
With the F-CPU the logic pipeline is limited to about 6 CMOS
gates. The organization so far looks good but putting the design
in a FPGA will mess up the timing because of the logic structure
used in the FPGA. Lets not worry about the speed of the pipeline
here because it is the relative speed of the stages that counts.
Everything done in the for speed FPGA will completely be undone
in the custom version. 
Reading the book "CMOS circuit design layout and simulation"
ISBN 0-7803-3416-7 and just other stuff the datapath layout is
still best designed by hand. Can such a layout (transistor
level) be merged with VHDL so that non-crital stuff and critical
hand placed logic both be used in the same layout?
Ben.
PS. looking a paper on carry skip adders ( grabbed off the web )
a sample 64 bit adder is about 18 unit delays. A adder delay is
3x the basic pipeline speed. I am guessing a carry skip adder
may be faster in the future because it can scale better for the
very latest in technology over the other kinds of adders.
  
-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
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