Re: [f-cpu] TLB resume

[nico <nicolas.boulay@ifrance.com>]

Michael Riepe a écrit :
> 
> On Tue, Aug 06, 2002 at 10:27:31PM +0200, nico wrote:
> [...]
> > >         - address space identifier (ASI; 8 bits was suggested)
> >
> > Could be an output and then we check it with an SR. But if it's an
> > input, we didn't to flush the tlb during a task switch !
> 
> The ASI was supposed to be an input. Together with the virtual
> address, it forms the lookup `key'.
> 

Yep !

> [...]
> > >         - supervisor access rights (RWX, 3 bits)
> >
> > i don't really understood the use of this one.
> >
> > If a process make a system call. It use a specif call that change the
> > mode (user-> superuser). Superuser (the kernel) could access to
> > anything. But the strangest thing is that superuser are the one that
> > could change the tlb content...
> 
> If supervisor mode is allowed to always access everything, you have a
> big security hole.
> 

Could you explain why ?

> [...]
> > >         - page size (4K << size, 6 bits)
> >
> > Page size are critical. How many memories could be acceded without a tlb
> > miss ? In x86 world, the pages are 4 Kb large. The tlb have between 32
> > to 128 entries : 512 Kb adressed. That's few !
> >
> > Intel introduice big sized pages (4 Mb) for framebuffer for example.
> > Linux use it for the kernel code (so there is no tlb miss inside the
> > kernel code).
> >
> > If the size of the page are bigger you could addresse more memories with
> > the same number of entries. But i could became hard for the pagging
> > system to find hole aligned with power of 2 adresse bits. A process
> > needs at least 3 pages (code, data, stack).
> >
> > Here is a top extract :
> [...]
> > Hurd guys advice to have 4 size : tiny for message passing (4 Ko ? what
> > ever the size, a message is message and most of them are small, so it
> > will use a page), medium size for code (64 Kb was the first idea), big
> > size for framebuffer and fat kernel (4-8Mo, 16 Mo) and very big for
> > memory hungry application (data based, a scientific tools,...) (256 Mo
> > !).
> >
> > So 4 sizes !  In the IA-64 arch, intel put 11 sizes !
> 
> Bigger address space, bigger pages. That's logical, isn't it?
> 

bigger waste, too ! That's the risk.

> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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