[f-cpu] Resume of Fcpu features

[nicO <nicolas.boulay@ifrance.com>]

I wrote a french article (good for prior art proof and money) about the
fcpu. This work will be used for the 18C3 conference, too. (if they
respond to my email !!!)

So the fcpu feature :
- 64 bits SIMD (extensible by power of 2) 
- 64 registers
- 32 bits instuctions word
- superpipeline
- none superscalare (4 ways max in the future)
- no OOO (no needs)
- so no register renaming (no needs too)
- no branch prediction (for the moment)
- associative memory between reg name and memory content to speed up
memory featch and load (but there is an hard trend how do we handel
memory alias ?)
- intentive use of cmove and cjump required
- RISCy instruction inst R1, R2, R3
- 2 adressing mode : immediat and register only.
- no register windows (handel the trap is an overkill, but maybe too
increase the number of register in the future, or we will used 64 bit
instructions word to access 65535 register ? why not ? There is enough
room ! ;p)
- The SRB to speed up register saving for trap handler, it could be used
for loading or saving memory from packet of register (packet of 8). But
it used mix of special register, and i have a problem where to put
return adresse (there is non stack in the fcpu !), we put it in R0 ?
- TLB very close to the processor but we use L0 cache to precheck the
TLB before effectively used the data.-> so L1 cache are physicaly cached

My question are : does i forget something ?

nicO
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