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Re: [f-cpu] Zen and the art of F-CPU assembler coding



> If we drop it (or maybe move it to a second pipeline stage and make it
> support *all* chunk sizes), there will be enough room in the ROP2 unit to
> add `n -> 2**n' decoders in front of it for 1-cycle btst/bchg/bset/bclr
> instructions that are more useful than combine, IMHO.

One more idea/question, the ROP2 3->4 decoder is placed in
xbar stage. If `n -> 2**n' decoders would take too many time,
at least immediate form (which is the most used one for bit flag
manipulation) can be done by moving decoders (or pipelinable part
of them) to xbar stage too.
Or do you know any important usage of non-immediate form
with significant savings from shift+and/or method ?

devik

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