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Re: Rep:Re: Re: [f-cpu] No latches, please !



> first, it's a bit smaller. Depending on the amount of control logic,
> the gain varies. The memory cell (4 transistors) requires decoding
> and clock buffering, IIRC the sxlib FF uses around 20 transistors.

Is the logic size anymore a problem? At 0.13u you can get about
200kgates/mm^2, and minimum size silicon for reasonable packages is
around 100mm^2. Usually the logic in current generation chips is small
grain in some corner of the chip and rest is memory. And memory is done
quite differently layoutwise depeding on memory technology and speed
(about 300-1600kbit/mm^2).

Optimizing few transistors/gates is not worth the job anymore. The problem
is becoming power usage, yield, design sizes etc. And to attack power use
usually gate counts rise quite dramatically (sounds odd but this is the
truth). For example some power saving cells have twice the amount of
transistors to fight with power leakage in the cell. Efficient signaling
between blocks also adds more logic, block level clock management also is
quite complex thing.

> in another mail Bruno spoke about a 16*64 cell that can work at 2.2ns,
> this puts the maximum operating frequency (.18u) at around 300 or 400MHz.

You have to remember that there are also different cell libraries for
commercial processes. Some libraries are geared for maximum performance
and consume more power and the yield might be lower. Then there are
lopower cells that are slower. These things are very difficult to predict
without real data and libraries. And those who have access to the data
have  NDAs so we have to be very careful what we speak (no excact numbers
only ballpark figures, no manufacturer names etc.).

--Kim

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