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Re: [f-cpu] testing



> With all this talk of testing -- why not a have nice 12 bit micro -
> micro computer add,nor,store,jc - instructions and have it test out the
> main F-cpu. If you really want to be sneaky have a core logic block
> tested by normal means of a minimal F-cpu that then tests out the rest
> of system. All that cache and main register file is a good bit of
> program space.

The problem is still the speed of testing. To get good coverage from the
edges of the chip huge amount of vectors is needed. This is same problem
that is visible between block and toplevel verification of chips. If
blocks are not well verified on their own it is almost impossible to
verify them from the toplevel.

Also normal tool flows do not fit into this kind of design. How do you
for example optimize the vectors this small CPU feeds into the design.
There are some formal tools (model checkers etc.) that can be used to
deduct the needed steps on chip edge to get it into certain state, but
those tools are slow and they can't optimize the vectors. If you create
one vector for each node first and then optimize them it would take years
of CPU time to first create the vectors :)

Some scripting and Solidify could do the vectors, but it can take minutes
for each node and if we have about 500kgates that means little over and
year of calculation. And then the duplicated patterns need to be found
etc.

What if we just use the existing ATPG methodology with scan chains. That
is known technology and well tested.

--Kim

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