Re: test (was: [f-cpu] No latches, please !)

[Juergen Goeritz <goeritz@oekomm.de>]

On Sat, 16 Feb 2002, Ben Franchuk wrote:

> Juergen Goeritz wrote:
> 
> > Other example: imagine a 500 processor cluster in an orbit
> > around Jupiter at high rad doses (I love these examples :)
> > 1/2 of your cluster sleeps to recover from radiation, the
> > other half is operating. Before sleep you test, after sleep
> > you test and during operation you test at regular intervals.
> 
> Nah... I would have the 500 cluster in orbit around the sun
> running a anti-matter production plant using solar energy. Anti-matter
> takes a hell a lot of energy to produce but could make inter-planetary
> travel possible. 

Why do you think it may be possible to produce anti-matter?
Hasn't there been detected an asymmetry in favour of matter
lately?

> The problem is that transistor size of modern logic is
> it too small to not glitch or fry from radiation. A machine with a 250
> ns
> memory cycle and 1 Meg of ram could be a practical size and speed limit
> for hard radiation. While I have not looked a 'Leon' I would expect to
> have
> error checking of some kind in the alu and memory circuits. That was one
> advantage the old decimal machines had, error checking codes.A parity
> bit
> may be a good feature to consider with transistor sizes getting smaller
> and the mean time between soft errors goes down.

Yes, but one has to distinct between the size and energy levels
of the parts hitting the device. It was pretty much analyzed by
some ESA (and probably NASA) activities. Around the earth this
effect is not the real big problem. But near the sun or jupiter
it will be a problem. Think there was an article stating some
of the defects caused to the sonde currently circling around 
jupiter which also took interesting pictures about vulcanism on
the moons.

One effect in the transistor is the buildup of a load in the
substrate layers that may damage the transistor. Think this is
caused by gammaray in combination with electric fields and is
building up constantly. When you remove the electrical field
the load slowly decreases again. But since I do not want to
crawl through the pile of documents again I have no figures.
Alpha & Beta radiation may be better shielded by other means
since they can really blow your chip structure.

But maybe one of the guys working directly at ASIC centers
could tell me whether it is possible to control the power
branches in SoC designs to really shut-down parts of it
directly onchip. And I mean a completely powerless state
not the usual idle power-down mode used to save power.

AND if it is possible to intermix coarse transistors from
1.3u or even heavier ones with the latest 0.08u techniques
on a single chip. 

JG

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