Re: [f-cpu] virtually or physically-addressed cache ?

["Marco Al" <marco@simplex.nl>]

From: "Christophe" <christophe.avoinne@laposte.net>

> Marco Al wrote:
> > From: "Christophe" <christophe.avoinne@laposte.net>
> > > Virtual or physical addressing ?
> > > -------------------------------------------
> > > (1) virtually-addressed caches (virtual tags)
> > >
> > > + do address translation only on a cache miss
> > > + faster for hits because no address translation
> >
> > Another plus to this method, its the only way to go with software
> > managed address translation AFAICS.
>
> But what happens if we have a L1 hit and get in fact a TLB miss
> (invalidation, read-only, etc.) ? our TBL would need to flush L1 to be
> synched with TLB before resuming the faulty instruction after a TLB
> exception.

There would not be a TLB as such, it wouldnt be software managed address
translation otherwise. For protection you probably want per cacheline
protection bits. Invalidation is simular to changing protection I guess ...
see section 5.6 of the paper "Uniprocessor virtual memory without TLBs." at
http://www.ee.umd.edu/~blj/

A naive implementation would have some "issues" obviously. For instance
without a shared global address space you have to flush the cache on context
switches, and even with it you probably wouldnt want to walk the cache to
change protection bits every time you made a switch. The paper mentions a
lot of problems and potential solutions.

Marco

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