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Re: [f-cpu] random number generator



hello,

gaetan@xeberon.net wrote:

Hello f-cpu world !

I'm looking for a real random generator for intensive tests on the floating point adder.
I would like to generate randomly a set of real numbers (single or double precision) and feed my adder with.
what is possible is to generate integers.
then you have to "build" the FP number.
If you can do this, it's ok.

now, there exists a lot of work on this matter.

The simplest thing is a LFSR but it is not adapted
because the correllations between the bits might
miss faults. Something a bit more complex is needed,
look at the table-based methods. Given an initial
set of 2^n integers, it will generate good quality bit streams.

Now here comes the critical question (i have faced it
when writing the random initialisation in VHDL) :
do we need to reset the counter everytime or do we want
a new bitstream each time ? I have chosen the second
solution for the VHDL case because a "static"
bit generator can miss errors.

A solution that can be practical is to manage a small
"entropy file" (just like under Linux). It contains
the 2^n numbers, can be exported/imported as text
with VHDL functions, and is read during each simulation
startup. If a test fails, the table is not written back
to the file and we can track where the error is.

how does this idea sound ?

I've found someone but i don't know if I could use them (licence conflict??):
http://tech-www.informatik.uni-hamburg.de/vhdl/packages/mathpack/mathpack.vhd
this is a MATH_REAL package for ones (like me) who doesn't have the expensive math_real from ieee.
the sentence "This package cannot be sold or distributed for profit."
is not compatible with "pure GNU" philosophy.
well, it's an *implementation*, and what you do is use it,
through a defined interface. so you can use it as you want as long
as you don't distribute it. You can mention in the source
that you have downloaded this library at this address,
so whoever doesn't have IEEE at home can use it.

Of course it would be better to have something that can be hacked
at will, but at least there's a temporary working solution.

I don't really need a complex one, just something to avoid me to type every constant...
and an other problem is the seed: is there a "time()" function in vhdl, or anythig else to "pseudo-random" initialize the generator...
I'm under windows so i don't have /dev/random >:o ...
the "entropy pool" in the file, as described before, looks like a good solution.
There is a POSIX interface layer for VHDL but that won't work under windows.

btw, i have found a way to use Simili 2.3 under windows :
i'll be able to look at your work but i won't have much resources
(PII 300MHz + 64MB) so i hope that your testbenches don't
require too much CPU time :-)

the random package in the source tree just read a file... i will use it if i don't find anything else but i don't really like it...
ok, i'll try to help you on that.
it might take some time but the entropy pool idea should be ok.

all suggestions welcome !

thanks,

so i go back to my adder

byebye
YG

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