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Re: [f-cpu] VHDL and delay estimation
hi !
gaetan@xeberon.net wrote:
Michael Riepe a écrit :
I don't think so. Actually, if you calculate `ss' like this, it won't
fit even without the half adder. But I don't know what's around the
circuit. Maybe there is room somewhere else.
just to know the cost of a xor (in fact the half adder): 2 gates deep?
yes, it's a conservative choice.
good night,
YG
/off2bed
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