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[f-cpu] by the way

by the way one other question:
ieee defines 4 rounding modes (round to nearest, to + infinity, to -infinity and to Zero), so i put a input in the architecture:
RoundMode: in std_ulogic_vector(1 downto 0); -- 00 : nearest, 01: zero, 10: +inf, 11: -inf
But how will it be implemented higher? special register changed by an instruction? or directly from the instruction?

I propose:
flags 19-18 (unused for the moment) : rounding mode
and for the instruction synthax:
no postfix : rounding to nearest (default)
".RPI" : Round to + Infinity
".RMI" : Round to - Infinity
".RZ" : Roung to Zero (or ".RZO")

And for Size postfix synthax (not defined for the moment in the manual), why not
.32 : single operation
.64 : double operation

so instruction would look like:
fadd.64 R4, R3,R2
for double float operation with round to nearest mode.

sfadd.32.RZO R8,R7,R6
for single SIMD operation with round to zero mode.

An other thing: how do you plan to manage exception when they occurs? I mean, when a exception occurs (ieee flag clear), the unit will ouput an exception flag, and the ieee standard wants it to stay raised untill an special instruction clear it...


~~ Gaetan ~~

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