Re: [f-cpu] ERIN32

[Yann Guidon <whygee@f-cpu.org>]

hello,

though your posts sometimes look off-topic, this one raised a question.
I hope that others will give their advices and share their experience.

> richard hartny wrote:
> 
>     I see some points made on circuit loading.  While at Sanders
> Associates Inc several years back; it was determined that a Logic
> design having a maximum fan-out of 7 loads had a good chance of
> surviving temperature testing over the military temperature range
which chance ? 100% or less ?

> of -55 to +125c.  In my design of the Erin32 I took special
> care to have a maximum load of 8.  In the chip design process;
> there is an Auto-buffer option - I always use it.
<snip> 
>     I will be very happy to answer any questions of the design.

so here we go.

When i did some ACTEL FPGA design, several years ago, the manual said
that a fanout higher than 8 was not recommended. On top of that,
the "compiler" (which processes the DesignArchitect hierarchical drawings)
would probably modify this but i wasn't told to what extent.

Currently, i try to limit fanout to 4. I think that it is a good balance
if we consider that the cell would get otherwise even larger (with a larger
output buffer) and the wire loading comes into play. I prefer to duplicate
the cell, like i did in the ROP2 unit (in the AND/OR combine operation).

I have read the discusion about the fanout trees and want to know how
this translates in this case. In the end of this call for comment, it
would be cool if a specification or design rule could be drafted/proposed,
addressing the widest range of tools and technologies.


> Regards
> Richard E. Hartney
WHYGEE
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