Re: [f-cpu] LSU or cache L0

[Michael Riepe <michael@stud.uni-hannover.de>]

On Fri, Jan 11, 2002 at 09:23:27AM -0700, Ben Franchuk wrote:
> Juergen Goeritz wrote:
> > 
> > It looks like someone should setup some compiler directive paper.
> > The more complex the compiler will get, the longer you will wait
> > for one to come that is capable of doing all this stuff. A new
> > processor is nothing without the compiler/debugger support. The
> > lastest example was one coming from Germany called Hyperstone
> > which got mixed size instruction length thus being able to not
> > have a pipeline stall at context switch with just a 2 word cache.
> 
> Lets not to forget to write a Assembler too. :)

I posted a semi-complete Unix-style assembler four months ago, and
Yann was working on another one. I also started writing a simulator
(for assembler testing and instruction set re-evaluation), but I was
interrupted by other things :(

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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