Re: [f-cpu] LSU or cache L0

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Juergen Goeritz wrote:
> 
> It looks like someone should setup some compiler directive paper.
> The more complex the compiler will get, the longer you will wait
> for one to come that is capable of doing all this stuff. A new
> processor is nothing without the compiler/debugger support. The
> lastest example was one coming from Germany called Hyperstone
> which got mixed size instruction length thus being able to not
> have a pipeline stall at context switch with just a 2 word cache.

Lets not to forget to write a Assembler too. :)

-- 
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html
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