Re: [f-cpu] statistics of direct indexing usage

[devik <devik@cdi.cz>]

>  From the little i know, the register set, as it is, is the main problem.
> it's a huge piece of silicon and i count on FC1 (a highly hypothtical thing)
> to solve this problem (among others). It's probably possible to adapt
> FC0 to reach 1GHz, but it's probably not worth it. It's better to
> target the design of the next architecture towards this barreer,

hmm .. I already though that 6 gates granularity is there
to go very fast. Probably the register set doesn't follow
the rule ?
PIII which can go 1.2 GHz AFAIK does 32bit add within 1 cycle
latency so they use higher gate-depth per stage than fcpu
which can do obly 8bits. (P4 uses 2 cycles).
Probably they have smaller/simpler register set inside ?

devik

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