Re: [f-cpu] Instruction census

[devik <devik@cdi.cz>]

> > that it doesn't trap - if it would like trap it stores the condition
> > in flag associated to the destination register.
> > When such value would be used it would then really trap.
> > Completion load can check the flag and jump to special stub
> > code to handle it.
> > It allows you to load *a in expression if (a) b = *a; without
> > change of side effect.
> >
>
> What is the différence between prefetch of x86 ? Is it the same
> difference between preload and prefetch ? Does not an L1 do the job ?

ld.a loads it into register. With prefetch you still have to
to L1->reg move which costs at least one cycle.
Because Itanium is 6-issue then 1 cycle is way too much because
it often make part of program twice slower. The trick is that
you can do:
// cycle 0
ld.a r1 = [r4]
st [r5] = r3
// cycle 1
ld.c r1 = [r4] // if this has to reload, other cycle is included after it
not r2 = r1

without it you have to do:
// cycle 0
st [r5] = r3
// cycle 1
ld r1 = [r4]
// cycle 2
not r2 = r1

ld.a and ld.s are ways to find more ILP needed for 6issue CPU.

> i particulary hate the r^1 adressing :) Is that easier to define paired
> register ? It through aways some flexibility but could you say to gcc to
> consider register as extended one (writing the result in a double sized
> register like x86 mess). For a 2r2w, the write port will be R2-R3, R3-R2
> is also true but could be avoided in a first time ?

the paired reg has the same problem unless it is used within expander.
combiner has problems with it unfortunately.

> > > C[i]=A[i]*B[i] or A+=V1[i]*V2[i] ?)
> >
> > no. It requires vectorizer which is not present in gcc yet.
> > But loop optimizer is planed to be rewritten and vectorizer
> > will be probably added too.
> >
> :( it seems so easy !

try to change loop.c in gcc. It might be possible to do it
once gcc detects all BIV and GIVs you can detect code like
A[GIV]=B[GIV] OP C[GIV] and modulo expand it during unrolling.

> > > (Be carfull on itanium patent !)
> >
> > which one ? so I know what things don't thing about at all .. :-(
> >
> arf. Itanium is a recent design so probably full of patent. All
> "inovation" in Itanium design is certainly soon patented.

ahh I thought you mean concrete patent - ld.a and ld.s are used
by other cpu like Alpha only not explicitly - Intel might patent
its explicit use IMHO.

> > BTW what is load-linked/store-conditional ?
> I don't think so or by an other chip maker.

you misunderstood the question, I asked WHAT is
load-linked/store-conditional .. I don't know the name.

devik

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