Re: [f-cpu] Instruction census

["Christophe Avoinne" <christophe.avoinne@laposte.net>]

load-linked/store-conditional :

instructions ll/sc that you can find in MIPS I think.

The main idea is to have a store that only occurs if we know there is no
store since the last load linked was called at the same memory place.

To emulate an IA32 XADD :

int XADD (int *slot,int delta) {
    int old,new,stored;
    do {
        asm ("ll %0,[%1]" : "=r"(old) : "m"(slot));
        new = old + delta;
        asm ("sc %0,[%2],%1" : "=r"(new), "=r"(stored) : "m"(slot));
    } while (!stored);
    return old;
}
here I choose the format "SC R1,[R2],R3" where R1 is new data to store at
address [R2] if that address was not dirty by a previous normal store or a
store conditional (R3 is not 0 if stored really occured).

Another emulation, IA32 CMPCHG :

int CMPCHG (int *slot,int *old,int new) {
    int value,stored;

    asm ("ll %0,[%1]" : "=r"(value) : "m"(slot));
    if (value != old) {
        *old = value;
        return 0;
     }
    asm ("sc %0,[%2],%1" : "=r"(new), "=r"(stored) : "m"(slot));
    if (!stored) {
        *old = value;
        return 0;
     }
    return !0;
}

----- Original Message -----
From: "devik" <devik@cdi.cz>
To: <f-cpu@seul.org>
Sent: Wednesday, January 15, 2003 10:37 AM
Subject: Re: [f-cpu] Instruction census



> > BTW what is load-linked/store-conditional ?
> I don't think so or by an other chip maker.

you misunderstood the question, I asked WHAT is
load-linked/store-conditional .. I don't know the name.

devik

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