[Fwd: Re: [f-cpu] FPU Adder....]

["gaetan@xeberon.net" <gaetan@xeberon.net>]

i had not forward my answer+question to the mailing list... sorry MR for 
receiving twice this message

-------- Original Message --------
Subject: 	Re: [f-cpu] FPU Adder....
Date: 	Mon, 05 Jan 2004 18:19:39 +0100
From: 	gaetan@xeberon.net <gaetan@xeberon.net>
Reply-To: 	gaetan@xeberon.net
To: 	Michael Riepe <Michael.Riepe@stud.uni-hannover.de>
References: 	<200312301614.hBUGEqh7004632@sivit6.org> 
<3FF32712.2040408@stud.uni-hannover.de> <3FF5C474.3010406@xeberon.net> 
<3FF5DBCE.6060103@stud.uni-hannover.de>



i'm rewriting the code which will operate with both SIMD size (32 and 64 
bits), but i'm still wondering if i should use iadd ou generic_adder for 
the mantissa operation...
for the exponent, i can understand it could fit into one cycle (at least 
for the 8 bit exponent, and surely for 11 bit exponent), but i still do 
not know if generic_adder generate
code that fit into one cycle (for the 23 bit mantissa and the 52 bit 
mantissa)...
if not, how can i "divide" the work to do an operation in 2 cycles? to 
treat 8 LSB first and then the MSBs for instance?

Michael Riepe wrote:

> Actually, using the components of the generic adder will be faster 
> than IAdd which needs one or two full cycles, depending on the 
> operands' sizes (and contains quite a lot of overhead, like variable 
> add/sub, saturation and carry-out circuitry). A dedicated 16-bit 
> subtractor -- which will be suitable for most floating-point formats 
> in use today -- shouldn't be deeper than d=8 (compared to d=12 for the 
> full IAdd unit) and can provide both 'b-a' and 'a-b' results at the 
> same time, so you'll never have to negate the result (which is costly, 
> too). The only drawback is that you'll have to insert one or two 
> pipeline registers yourself. On the other hand, the generic adder is 
> prepared for that: Its components are only one or two gates "deep".
>
> > For the moment i use the iadder for everything, but i will remove it 
> > for exponent at least... but is it possible to
> > instantiate a 32 bits iadder (for the moment i know, it is NOT) for 
> > the 23 bit mantissa, because higher bits
> > are not used and for the moment, it is 0000...0000 + 000.....0000 (32 
> > bit SIMD operation)....
>
> That's another reason why you should use the generic adder. With the 
> package, you can build adders of any size. E.g. one of my testbenches 
> instantiates a 939-bit adder :-) Most other Units I wrote use 
> functions from the generic adder internally as well -- including IAdd, 
> IMul64 and IDiv64.
>
> Michael.

--

~~ Gaetan ~~
http://www.xeberon.net






--

~~ Gaetan ~~
http://www.xeberon.net



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