Re: [f-cpu] Coding for Synthesis

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

>> - pipeline enable:
>>
>>    If your unit has more than two pipeline stages, you probably want
>>    to chain the enable signal. That is, the enable signal `travels'
>>    through the pipeline together with the data `wavefront' (I used
>>    that trick in the IMU in order to save power). To do so, provide an
>>    `enable out' signal in each stage:

But would not optimzation refactor the gates down to a single level?
As for just what the enable logic is give me a schematic any day
as it looks like the enable signal is undefined most of the time.


Also two resets for a CPU may be useful. Power on reset -- level
sensitive and gated with the system clock. Master reset that edge sensitive
and povides a soft reset. A jump/call to address 0 could provide a
RESET trap to kill that thread.



-- 
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html

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