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Re: [f-cpu] f-cpu simulator



hi !

jaap stolk wrote:
> 
> i uploaded:
> snapshot_jws_16_07_2002.tar.bz2 to:
> http://f-cpu.seul.org/~f-cpu/new/
ok i got it and will look at it.
The files you first sent me seem to be ok
though i did not yet compile them.

> it's just a little test of last weekend,
> but it compiles, and can simulate ASU and
> INC instructions including xbar and register set.
wow.

> see the /c/jaap.txt file for more info.
> 
> jaap.
> 
> yg, it now shows all registers, and waits for
> enter after every stage.

i do not want to stop your helpful efforts but i have
a problem with the current testing workflow, a solution
would be to rewrite some things...

The problem is to be sure that all versions (C, VHDL etc.)
are coherent with the manual's description and (more importantly)
with each others. This way, any input in the C version will
return the same result for all other versions (if someone wants
to make a Verilog version, or whatever).

The idea is to do a pattern generator for each unit,
and send it to all the testbenches. The results will then
be compared (a diff will be ok) and equivalence of the
versions will be ensured.

I don't have a clear idea yet of how to do this, i want
to avoid "naughty hacks" at any cost. I don't want to be
forced to rewrite things whenever a new thing is implemented...

one "clean" way would be to create another subdirectory,
maybe "patterns", so "c" and "vhdl" could read the generated
files. The script would then run "diff" on both results.
Another solution is to generate the patterns containing
input and expected output, so each testbench can catch
the inconsistencies themselves, but it's more complex.
Not to mention that the input format for every unit
changes (the interfaces differ) so a library must be
written in each langage to read and compare the test patterns :-/

WHYGEE
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