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[f-cpu] Free synthesis tool for Verilog and other links
- To: f-cpu@seul.org
- Subject: [f-cpu] Free synthesis tool for Verilog and other links
- From: Michael Opdenacker <zumbi2@netcourrier.com>
- Date: 17 Jul 2002 19:44:00 +0200
- Delivered-To: archiver@seul.org
- Delivered-To: f-cpu-outgoing@seul.org
- Delivered-To: f-cpu@seul.org
- Delivery-Date: Wed, 17 Jul 2002 13:45:23 -0400
- Reply-To: f-cpu@seul.org
- Sender: owner-f-cpu@seul.org
Hello,
As I told some of you last week in the LSM event, a free synthesis tool
exists for Verilog (unfortunately not for VHDL):
http://icarus.com/eda/verilog/
Here is also a nice page full of useful links, for those who may not
know it:
http://www.eedesign.com/resources/opensourcelinks.html
Good luck for your great project!
@:-)
Cheers,
Michael.
--
Michael Opdenacker
http://michaelo.free.fr/
MATH AND ALCOHOL DON'T MIX!
Please, don't drink and derive.
Mathematicians
Against
Drunk
Deriving
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