Re: [f-cpu] Free synthesis tool for Verilog and other links

[Just an Illusion <illusion_to_net@yahoo.fr>]

Kim Enkovaara wrote:
<cut>

>
>The equivalence of the different block architectures can be checked with
>formal tools to make verification of different versions easier. The
>problem with this approach is that there are no free formal tools, and I
>doubt that there will be for a long time.
>
False, you can find few of them, but they are limited : in performance, 
on input language support...
See my previous answer with the Alliance link.

Follow a non exhaustive list :
Alliance
vis & sis
(I know than I have forget 1 or 2 more minimum but I could remember 
their names)

Cheers,
Just an Illusion

-- 
______________________________
"The matrix is my world, I am a shadow.
Shadow in world, shadow in life. Don't try to keep me,
I am a Corpo's Killer.
Don't follow me or die..."
		The KingWalker - 1996



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