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Re: [f-cpu] Free synthesis tool for Verilog and other links

> I allways thought BOTH were stupid languges : VHDL and Verlog.
> The irony is for best layout you still need to design the layout
> by hand -- CLB placement or Transistor masks.

They are adequate languages for the design, not optimal. It is not usually
feasible to design everything at gate level, imagine how long it would
take to make 5M gate chip with schematics. Even with high level VHDL
description it is a huge task. It much faster to manually fiddle with the
most critical blocks and let the automatic generation handle the
noncritical parts.

> almost have to write your own stuff. My question is that the F-CPU is
> to be tested with a FPGA design but will it still be portable to a
> mask layout? What if I want optimize some logic by hand can I still
> get at information generated after several versions of compilation?

Easiest way is to code first versions of FCPU at quite high level with HDL
languages. From that description it is quite easy to synthesize quite good
versions of the chip for testing. Even if the speed is 50% of the optimal
speed it is good for the testing. After the design is working and
tested then different architectures of the block can be made to optimize
the behavior for different needs (ASIC/FPGA etc.). For example with good
synthesizer best implementation of multiplier can be c<=a*b style
structure. Synplify for example has excellent multiplier library for
FPGAs or if available used HW multipliers from the fabric.

The equivalence of the different block architectures can be checked with
formal tools to make verification of different versions easier. The
problem with this approach is that there are no free formal tools, and I
doubt that there will be for a long time.

Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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