Re: [f-cpu] Free synthesis tool for Verilog and other links

[Ben Franchuk <bfranchuk@jetnet.ab.ca>]

Just an Illusion wrote:
> Hi,
> 
> I have yet tested this tools (on this version, if well remember), but it 
> seems have too many limitations on supported verilog subset.
> It's why we have decided (in my company) to do not use it. 
> For information the Alliance project from the lip6 laboratory (from 
> university of Jussieu in France) have a free synthesize tool with a 
> capability of vhdl keeping. But the rtl vhdl subset is too limited to 
> support a "real" industrial model.
> if we want use this type of tools (on the project), we need well
> identified the input restrictions on the language, and code with it.
> 
> Cheers,
> Just an Illusion

I allways thought BOTH were stupid languges : VHDL and Verlog.
The irony is for best layout you still need to design the layout
by hand -- CLB placement or Transistor masks.
But did not the limited vhdl subset in Alliance permit generation
of gate level constructs by calling C routines? The problem is
how much open source is the F-CPU? If you can't have visible information
from HDL source to transistor masks (or raw gates) how can you 1) find bugs ,
2) Improve layout 3) have open source from libraries used?
Right now using FPGA's the tools limit you to gates and FF's for portable
work. While HDL's seem to permit simulation and ease of coding, you still need
several layers of abstraction that the tools don't permit you so still
almost have to write your own stuff. My question is that the F-CPU is
to be tested with a FPGA design but will it still be portable to a
mask layout? What if I want optimize some logic by hand can I still
get at information generated after several versions of compilation?
-----
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html

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