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Re: [f-cpu] Free synthesis tool for Verilog and other links

>   That is true. I was just reading on the web that the biggest problem
> with software is keeping the comments up to date. Do you have a
> procedure for that?

Documentation is always the problem. One critical thing is that the design
specifications should always be the master documents. Usually the code is
considered to be the main documentation, but in big project it is
impossible to read everybodys code.

Internal block implementation documentation is not so critical if the
interfaces are well documented between the blocks. Interfaces are
important for the other designers and for the verification engineers.

>    I can do that with schematics too. I will re-state the question.
> Is the net-list in a form that can still be read by people if you want
> to tweek the code by hand?

Usually different tools destroy the hierarchy inside the netlist at least
to some extent. For big chips manually fiddling with the netlist is not
fun task to do. I wouldn't even try that without formal tools to check
what the change really did. And even small manual netlist changes can
make interesting problems in layout.

Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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