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Re: [f-cpu] Conditionnal Load and Store
Christophe Avoinne wrote:
> ----- Original Message -----
> From: "Yann Guidon" <email@example.com>
> > hi,
> > <snip>
> > conditional loads/stores are a corollary of the conditional moves.
> > IIRC it appeared that these instructions were in fact needed,
> > when we were discussing about the semaphores done with LL/SC.
> > "Store conditional" is this thing.
> > By the way : condition 3 is still reserved for FP, but we could
> > simply connect it to the LSU : LL/SC would then not need any specific
> > opcode. it sounds easy and logical, what do others think ?
> I don't really understand how you plan to do so.
> LL [r1],r2 ==> loading [r1] in r2 and set a lock bit in matching LSU entry.
> SC r2,[r1],r3 ==> storing r2 in [r1] if lock bit in matching LSU entry is
> set and set r3 to 1, otherwise just set r3 to 0. Then lock bit in matching
> LSU entry is reset.
> IF (r3 == 0) JUMP ... // goto retry;
> As you can see, you need to set this special bit with a LOAD operation and
> check it and report it in register with a STORE operation
> So I wonder how you can use condition 3 with LOAD/STORE to do so since STORE
> would also need to report if storing really occured or not..
mmmh i see.
My idea goes as follows :
The condition is an "attribute" of the condition register, which
can be tested with move and jmp as well. Like the "zero" flag,
it is regenerated everytime something related happens.
So the information of whether the store really occured needs not to
be duplicated. The only "problem" is that it is a "volatile" flag,
so it might yield false negatives.
Your idea is a bit different because it includes "persistent" data.
it has drawbacks and advantages. the drawback comes from the fact
that the decision history is made "static" or "persistent".
One problem is that the condition in your code is at the place
of R2, and a specific SC is not desired if we add the generic
"conditional store" instruction.
The real big problem is that in this instruction, the condition
and the pointer are the same register => should not need to be
There is something i miss, but i don't know what...
> NOTE: the given syntax for LL/SC is absolutely not mandatory. They are just
> an example but the idea still remains the same.
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