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Re: [f-cpu] What's wrong here?



hi,

Michael Riepe wrote:
> Ok... can anybody tell me what's wrong with this function?
> 
>         function inv_word(A : in std_ulogic_vector) return std_ulogic_vector is
>                 variable L : natural := A'low;
>                 variable H : natural := A'high;
>                 variable B : std_ulogic_vector(H downto L);
>         begin
>                 for i in L to H loop
>                         B(i) := A(H+L-i);
>                 end loop;
>                 return B;
>         end function;
> 
> Hint: consider the possible index ranges of the argument.

i've seen a post on comp.lang.vhdl (Wed, 10 Jul 2002)
about this problem. Since bit reversing is often an issue,
i have archived it. The conclusion was :

Jonathan Bromley wrote:
> 
> someone wrote...
> 
> > temp : std_logic_vector(N downto 0);
> > a: std_logic_vector(N downto 0);
> >
> > a(a'high downto a'low) <= temp(temp'low to temp'high);
> 
> Nope, sorry, doesn't work.  Bad slice direction on the right.
> 
> Renaud is right;  you must simply copy the bits, one by one,
> probably using a 'for' loop.  Synthesis should have no
> trouble with this, and will just hook the right wires together.
> 
> My favourite way to do it exploits the VHDL'93 attribute
> REVERSE_RANGE and saves you the trouble of doing any
> explicit arithmetic on the subscripts:
> 
>   function reverse_bits(a: in std_logic_vector)
>     return std_logic_vector
>   is
>     variable a_rev: std_logic_vector(a'REVERSE_RANGE);
>   begin
>     for i in a'RANGE loop
>       a_rev(i) := a(i);
>     end loop;
>     return a_rev;
>   end;
> 
> and then you can do things like this...
> 
>   signal a, b: std_logic_vector(7 downto 0);
>   ...
>   a <= reverse_bits(b);
> --
> Jonathan Bromley
> HDL Consultant / DOULOS - Developing Design Know-how


>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
WHYGEE
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