Re: [f-cpu] New snapshot for EU_INC and EU_CMP

[Etienne LABARRE <etienne.labarre@gadz.org>]

On Tue, Jul 30, 2002 at 01:04:30AM +0200, Michael Riepe wrote:
> On Mon, Jul 29, 2002 at 08:48:13PM +0200, Etienne LABARRE wrote:
> > Hi all,
> > 
> > New snapshot include a lot of changes and features :
> > 
> > INC unit and CMP unit are now two different units, for simplify and
> > decrease latency
> > 
> > Both units are based to the same component : find_lsb
> >  It's a binary tree for find the first null lsb in a word.
> >  It supports SIMD operations (size of chunk = 8, 16, 32, 64, 128, 256
> >  bits)
> >  It's based to only one function : and_reduce. It's is a standard
> >  function of ieee.std_logic_1164 library.
> 
> Did you find source code or documentation for package std_logic_misc?

???? It's standard library. Packages std_logic_1164 and std_logic_misc
are available with all vhdl tools.
(For example, with Simili, in Simili_dir/lib/ieee/stdlogicmisc.vhd)


> 
> I noted that you use ieee.numeric_std in your designs, which is a
> no-no. Or did you include it by mistake?

Oop's ! It's an error. My code don't need ieee.numeric_std... I have
forgotten to remove this line.

> 
> >  Latency of find_lsb is not exactly know, but i can estimate this
> >  to 3 level of 4-and, and 1 level of mux, or more exactly 2 level of
> >  8-and, and 1 level of mux. The precise latency is not important,
> >  because max latency will be fixed by timing constraints during synthetisis process.
> >  (It's an explain of my choice of standard function. "Just an
> >  Illusion"
> >  will can explain this more easy that me, i think...)
> 
> I'm afraid that a timing constraint will `blow up' the unit.

The problem of "6 levels of 4 and gates" is to depend to final
techno. 
I think taht this criteria is ok for FPGA techno, but not optimized for
the others.
I call standard functions, because synthetisis tools will have (i hope) available 
pre-routed (and optimized) functions for chosen technology.
==> the code don't must depend to techno.


> BTW: for 256 bits, you need *four* levels of 4-and.

Exactly, but 6-levels criteria is for 64 bits only.

> 
> > For INC unit, the data flow is :
> >  1 level of mux
> >  find_lsb : 3 level of 4-and, 1 level of mux
> >  1 level of xor
> >  2 level of mux
> >  total is 8 levels.
> >  Critical datapath is only for ABS operation.
> > 
> >  Supported operations :
> >  INC, DEC, NEG, ABS, LSB0, LSB1
> > 
> >  All operations are tested by my testbenches.
> > 
> > For CMP unit, the data flow is :
> >  1 level of xor,
> >  1 level of mux,
> >  find_lsb : 3 level of 4-and, 1 level of mux
> >  2 level of mux,
> >  total is 8 levels.
> >  Critical datapath is for CMP, MIN, MAX, SORT operations.
> 
> I doubt that you can get away with 8 cycles. From my experience, 64-bit
> CMP alone needs 1 level of 2-xor, 3 levels of 4-and, 1 level of 2-xor,
> 1 level of 2-and plus 3 levels of 4-or, giving a total of 9 levels.

Hmm, i have perhap's made an error. Can you look at my code ?

Etienne.

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