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Re: [f-cpu] CMP

hi !

Ben Franchuk wrote:
> richard hartny wrote:
> >    For what its worth;
> >
> >     I use the equivalent of an SN7485 Comparator for a 64 bit result of EQU, AGB, and ALB.  Requires 113 Logic cells of the Eclipse family of FPGA devices.  It requires 7 logic levels and executes in 10.2 NS plus setup time of three DFF's.  I can test and Branch on each of the registered outputs.
> >     If my Canadian counterpart (Ben) will send me his mailing address, I will send him an VHDL manual that I will never use.
> >
> > Dick Hartney
> I would have used a adder as I forgot about the 7485 style comparator.

that is also my proposition. the ASU has a "saturated mode"
and the output (unsigned mode ?) can be used to control
a CMOV. Better : if there was the necessary wiring or mode,
a SIMD version would be possible and the resulting bitfield
would be used in a MUX instruction. Then  MIN, MAX and SORT
would require 2 or 3 instructructions but there would
be no need of another unit.

But Michael knows his unit better than me. I simply wish that
the original "sub" with saturated output was implemented :
MR implemented a simple bit (which is logical, in a sense)
but a "-1" output would have been useful to emulate CMP.

PS: the ADDSUB instruction is very useful in DSP, and much simpler
to implement than what nicO proposes...
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