Rep:Re: [f-cpu] New snapshot for EU_INC and EU_CMP

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

Most of the time typical cell are NAND and NOR, to use AND gate
synthetiser could have to use NAND+NOT gate. It's very technologicaly
dependent (FPGA use lut of something as 8 inputs and 2 outputs, it's a
kind memory : 8 adress bit and 2 data bit, so every function of 8 inputs
have the same timing).

Then came the fan out problem. If the fan out is too high, the
synthetiser use bigger gate to drive higher current or use tree of
amplificater (inverter or not). This could be done also after
place&route if the wire is too long.

nicO
 
-----Message d'origine-----
De: Michael Riepe <michael@stud.uni-hannover.de>
A: f-cpu@seul.org
Date: 31/07/02
Objet: Re: [f-cpu] New snapshot for EU_INC and EU_CMP

On Tue, Jul 30, 2002 at 05:44:33PM -0600, Ben Franchuk wrote:
> Michael Riepe wrote:
> 
> 
> > Therefore we only use elements that are supposed to be available
> > everywhere: and/or gates with 2...4 inputs, 2-input xor gates,
inverters
> > and muxes. With the famous `6 Gate Rule', any of them count as 1
gate.
> > Bigger elements (like an 8-input and gate) count as 2 or more gates.
> > 
> > After the first synthesis experiences, I later added another rule:
> > 2-input xors count as 2 gates, and the sum of gate delays must not
> > exceed 10. I call this the `6G/10T' rule.
> 
> What about inverted inputs? Do they count as a gate and what about
> flip/flop set up and delay times and what memory elements can
> one count on.

I count inverters as gates.

Since it's a `rule of thumb' that applies only to the combinatorial
parts of the F-CPU, flipflops are not covered.

Memory elements haven't been interesting for me because I currently
deal only with the execution units, not with caches or the register
set.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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