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Rep:Re: [f-cpu] New snapshot for EU_INC and EU_CMP



"Some" people beleive if as much effort will be put in designing a goog
CAML compiler it could go faster than a c++ compiler.

Why because instruction are at a very high level and the semantics have
no side effect : so a lot of optimising could be done. (imagine what
could be done if C language support vector operation as matlab, we could
use SIMD of every size we want and do strip mining and so one.)

That's the same thing in VHDL if you directly use AND gate, the
optimiser will have great problem. If youre code are "simple" it could
find lot of think to speed it up.

SOI technology didn't have the same difference in speed for large gate
than classic silicium (8 input AND isn't so slow compare to a 2 input
AND). 

nicO

-----Message d'origine-----
De: Michael Riepe <michael@stud.uni-hannover.de>
A: f-cpu@seul.org
Date: 31/07/02
Objet: Re: [f-cpu] New snapshot for EU_INC and EU_CMP

On Tue, Jul 30, 2002 at 10:50:44AM +0200, Just an Illusion wrote:
[...]
> >Did you find source code or documentation for package std_logic_misc?
> >
> The source code, of course. If some one need it, I can send it.

Yes, please.

> Like Whygee has previously said me this is not a ieee package (it's 
> copyrighted Synopsis), it is why I have never said than it is a 
> normalized package of ieee. But in the header of the package, Synopsis

> give right to use this package without restriction.

Hmm... someone claimed that it is a standard package. That was
obviously wrong.

[...]
> >I'm afraid that a timing constraint will `blow up' the unit.
> >BTW: for 256 bits, you need *four* levels of 4-and.
> >
> If your target techno have it. More the timing can change if your
target 
> techno have native 8-and or more.

We can't rely on that.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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