Re: Rep:Re: [f-cpu] parse VHDL code to create documentation

[Michael Strothjohann <strothjohann@rheinahrcampus.de>]

Kim Enkovaara schrieb:
> 
> On Wed, 27 Jun 2001, Michael Strothjohann wrote:
> 
> > my opinion: please have in mind: fsms with more then 10-15 states
> > are easier to work with when there is a textural (vhdl)-description,
> > your display is probab not able to show all states of your fsm at once.
> 
> In good state machine tools (Renoir=HDL Designer) there are no problems to
> create hierarchical states etc. The graphical reprsentation of FSM is very
> intuitive for human reader and it's easy to notice missing states etc.
> 
> After I really learned how to use the FSM tools I can do state machine
> much faster with them and with less errors. For example SSDRAM control
> state machine is quite complex, but I did the first version in one hour
> and it worked quite well.
> 

Hi Kim,
you are right, good state machine tools are good ( as the name says ) 
You are using Renoir ? How much you have to pay for it ? 
The common use of Renoir is to create state machines. 
Nico asked for a (low cost) tool to go the reverse direction, 
generating state-graph from vhdl. Renoir will do that,
esp. in the simplified case Nico mentioned in his mail.

michael strothjohann
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