In order to stop the fruitless register set discussion before it goes off again, I created several versions today: - one based on latches - a `banked' one based on 8x64 bit SRAMS (8 banks) - an 8-way `interleaved' one based on the same SRAM component - a transistor-level custom implementation The first and last items on the list should both be stall-free. The banked one isn't really an option because groups of 8 consecutive registers live in one bank (which will cause a stall every time there is a 2w instruction). In the interleaved version, register <n> is placed in bank <n mod 8> which is much more reasonable for the F-CPU. As usual, a testbench is included, as well as a simple-minded SRAM implementation (in case you want to simulate the units yourselves). Now go ahead and show me numbers, please. -- Michael "I did it again" Riepe <Michael.Riepe@stud.uni-hannover.de> "All I wanna do is have a little fun before I die"
Attachment:
fcpu-mr-regfile-20030616.tar.gz
Description: application/gunzip