Re: [f-cpu] second order prefetch in FC0

[Yann Guidon <whygee@f-cpu.org>]

hi,

devik wrote:

> > - Alpha 21264 uses data and instruction cache chaining (i don't
> > remember the right term).
> >  Each cache line contains 2 physical addresses of the last two memory
> > accesses
> >  after the cache line was used. This speeds up linked lists because in
> > the case
> >  of the cache line being used, the cache mechanism will prefetch the 2
> > cache lines
> >  referenced by the tag.
> > But, as i presume, these methods are certainly completely mined by patents.
> >    
> I just looked USPTO and didn't find such patent.
it's surprising but not improbable.
patents are now complex strategies and they have probably
made a string of patents to cover all parts and aspects,
rather than 1 patent describing the whole stuff,
just to be sure that there is no possibility to bypass the patent.

> Also in 21264 hw
> manual is no such data in cacheline ??
>  
or maybe it was 21364.

If it is possible to do, it will probably be implemented in FC0
but i don't want to take risks.

> devik
>  
YG

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