Re: [f-cpu] Status quo

[whygee@xxxxxxxxx]

Hi Ben,

Le 2015-03-28 15:49, ben a ÃcritÂ:
> On 3/28/2015 3:07 AM, whygee@xxxxxxxxx wrote:
> >      (BCD has a different carry propagation than plain binary)
> Try Excess 3.
but then you have to mix two kinds of results.
selecting from two different carry chains adds gates and delay,
either as a fanout tree or a fanin tree,
in the most critical datapath (the add unit).

> > Furthermore, you names IBM, as "real" computer. What line/family ?
> > Those that have explicit BCD support are designed for legacy execution
> > of COBOL.
> > If you want to make financial computing, it's your right...
> Funny that still sells BIG COMPUTERS.
> I was thinking large scientific computing using *large* numbers.
IBM sells several kinds of "mainframes" and "supercomputers",
most are using 64 bits (like F-CPU). Intel uses 80 bits FP
and some accumulators may be larger but for us right now,
"bigger is not better". For me the name of the game is "freedom"
and I try to design stuff that anybody can use easily.
It's not the strong point with F-CPU so far.

> Streamlining is fine, but regardless cache memory not raw gate speed
> is the limiting factor today.
It depends, in ASIC probably, however what are the odds one of us can
go to a fundry soon ?
For now we can use FPGA. I stick to the ProASIC3 family because the
gates are very similar to ASIC precharacterised gates and it exposes the 
inherent
latencies better than the competitors.
In FPGA the speed ratio between SRAM and logic is a bit different.
SRAM blocks are already optimised.

Anyway, in both cases, the real bottleneck is the I/O pins and
the external memory interface... Fortunately the latest FPGA
generations have decent DDR2 or DDR3 interfaces. The Igloo2 is
a pretty nice chip that supports this and I have already planned
to use it, along with ProASIC3 for smaller, cheaper designs.

I'm fortunate to be able to use, create and develop technologies for my
work with the ultimate goal to reuse them for this project :-)
yg
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