Re: [f-cpu] Status quo

[whygee@xxxxxxxxx]

Le 2015-04-01 01:46, Christophe Avoinne a ÃcritÂ:
> for zero extension of 8, 16 or 32-bit word into 64-bit word, a bit
> field extraction instruction is enough:
>
> x86                  <=> new CPU
> movzx rax, al <=> BEXT(ZX) r0, r1, 0, 8 : r0[63-8] = 0, r0[7-0] = 
> r1[7-0]
> movzx rax, ah <=> BEXT(ZX) r0, r1, 8, 8 : r0[63-8] = 0, r0[7-0] = 
> r1[15-8],
> movzx rax, ax <=> BEXT(ZX) r0, r1, 0, 16 : r0[63-16] = 0, r0[15-0] = 
> r1[15-0]
> movzx rax, eax <=> BEXT(ZX) r0, r1, 0, 32 : r0[63-32] = 0, r0[31-0] = 
> r1[31-0]
>
> it could be interesting to have a bit field extract with sign extension 
> as well:
>
> x86                  <=> new CPU
> movsx rax, al <=> BEXTSX r0, r1, 0, 8 : r0[63-8] = r1[7], r0[7-0] = 
> r1[7-0]
> movsx rax, ah <=> BEXTSX r0, r1, 8, 8 : r0[63-8] = r1[15], r0[7-0] = 
> r1[15-8],
> movsx rax, ax <=> BEXTSX r0, r1, 0, 16 : r0[63-16] = r1[15], r0[15-0] = 
> r1[15-0]
> movsx rax, eax <=> BEXTSX r0, r1, 0, 32 : r0[63-32] = r1[31], r0[31-0]
> = r1[31-0]
>
> It would also be fine to have :
>
> BEXT[S|Z]X r0, r1, r2, r3 : r0 is destination (write-only), r1 is
> source (read-only), r2 is lsb position (only-read), r3 is bit count or
> msb position (only-read)

I just checked the latest manual I have (version 0.2.7, see
http://f-cpu.seul.org/cedric/unstable/ ) and no bitfield insert/extract
is found...

But I also have the feeling that feature creep is to be avoided this 
time.
By wanting to do too much, I think the implementations would have been 
too slow...

Anyway, the manual contains a lot of interesting stuff that we'll reuse.
Then, specific cores will implement a certain set of features, depending
on their purpose and workload type.

> if too many read registers, merge lsb and msb into one register :
> r2[5-0] = lsb, r2[11-6] = msb or count.
>
> Bit field insertion :
>
> BINS r0 (read/write), r1 (read-only), lsb, msb or count ?
> BINS r0 (read/write), r1 (read-only),  r3 (lsb ? read-only),  r3 (msb
> or count ? read-only)

I think it's not wise to pack the operands in a register.
What would happen in SIMD operands ?

For extra registers or operands, I came up with using register#+1
but with my experience now, I think it was not such a bright idea,
so I'd use register# xor 1 (negate the LFB).

Doing +1 also negates the LSB so the register numbers are consecutive,
but the other bits are modified, with might create more issues than
it solves for more sophisticated designs...

As we're going to use FPGA, there are less opportunities to play with
gates and transistor tricks.

yg
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