Re: [f-cpu] whygee's Nth slaughtered ROP2 version

[Josh Fender <fender@ecf.utoronto.ca>]

On Sun, 25 Nov 2001, Yann Guidon wrote:

> Josh Fender wrote:
> >   On a slightly different note, I could test the unit in a real FPGA if
> > you have any test vectors.
> 
> i am about to do it, it should be ready within a few days.
> however, i do test vectors for VHDL testbenches, not FPGA tests :
> will you be able to adapt them ?

Sure it shouldn't be to hard.  The test system I use allows automatic
generation of circuit ports that can be written to and read from the
attached sun.  So long as the vectors are easily read from a C program
then it will be no problem.

- Josh


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