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Re: [f-cpu] Re: La MMU du f-cpu

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Subject: Re: [f-cpu] Re: La MMU du f-cpu
From: Yann Guidon <whygee@f-cpu.org>
Date: Mon, 17 Nov 2003 18:44:05 +0100
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hi,

Pierre Tardy wrote:
<snip>

The next steps may be to implement the Fetcher then the LSU then the caches.. At this time, I 've no idea  how long it can take us.

greets,

I have written about the LSU because we spoke about a simulation that would
be more or less acurate from the memory bus point of view. Because
the LSU & fetcher cache stuffs, this has an important impact.

Now, if you don't care about modeling the bus transactions, don't worry.

YG

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References:
- [f-cpu] Re: La MMU du f-cpu
  - From: Pierre Tardy <tardyp@free.fr>

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