[f-cpu] Compagnon cpu

[nicO <nicolas.boulay@ifrance.com>]

I just had a hard discussion with whygee about a new idea.

I have speak with a guy who write code for HURD. Compare to Linux,
context switch is a real problem for microkernel OS (usualy there is 3-4
task running in the same time). So i have a proposal to speed up such
thing.

I propose to introduice a very simple cpu which control the "main" fcpu.
I think of kind of a simple LEON (wihtout mul and without div) or a fcpu
without SIMD stuff, without FPU, without mul,...

This cpu could be seen as a ressource for the kernel only. It's no seen
by user. There is no virtual memory, and it receive all the interrupt
and manage all DMA access.

This compagnion could access to the register bank of the fcpu and it
could freeze the fcpu pipeline.

If the fcpu have a double register bank (shadow register), during each
access to the kernel, an other task could be run during the kernel
traitement immediately.

The idea is that this chip is very small compare to a second fcpu and
have a direct access to the (some) internals registers.

So usualy, interrupt handler are as small as possible but there is some
trash in the cache and the context switch.
(usualy to reduice the CDP the L1 cache use virtual memory (no penalty
to access the TLB in case of cache hit) but it that case in each context
switch the entire L1 cache _must_ be invalidate )

So the interrupt handler could be run only by this compagnon cpu. In
that case, we could reduice a lot the context switch penalty.

What do you thing ?

nicO
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