Re: [f-cpu] Bit Shuffler (Take 2)

[Yann Guidon <whygee@f-cpu.org>]

hi !

nicO wrote:
> Yann Guidon a écrit :
> > hi,
> > Kim Enkovaara wrote:
> > > On Thu, 27 Sep 2001, Michael Riepe wrote:
> > > > Wondering whether it's faster now,
> > > I hate to dissapoint you, but this new version is slower. It got 56MHz in
> > > the synthesis run for the same chip. I'll try to run the whole Xilinx flow
> > > to the different versions at some point. But the synthesis results usually
> > > correlate quite well to the actual results. Especially if some
> > > floorplanning is done.
> > so what is the cure, doctor ?
> Should i suggest to try to make the mul with mul 8*8 entity ? Synplicity
> use very high level optimising schem (it doesn't try to simplify at the
> gate level but at the structure level, that's why it's faster and more
> performant than the other fpga compiler). Our [michael;p] SIMD 64 bits
> mul should be quicker with basic 8 bits bloc. But this could be only
> true with fpga.

probably. But ... what about the shifter ?

> nicO
WHYGEE
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PS: i don't want to start another off-topic thread but i can't resist
to say that i have also acquired a SCSI recording rack (Yamaha CBX-D3)
for 150FF :-) but Surcouf (the store where i got it) made me pay the
necessary accessories for a very high price :-( (SCSI cables, AC adapter,...)
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