send me your test1.sym and I will run it for you.
Steve Meier
Oh, I forgot to include it. Sorry. Here it is!
/Arvid
On Thu, 2006-07-20 at 18:43 +0200, Arvid RosÃn wrote:
Ok. I am not sure what that means as I am not familiar with the PCB backend.
What happens if you run in on the top-level file (top.sch), which includes test.sch as a subnet?
/Arvid
Steve Meier skrev:
When I run gnetlist -gPCB test.sch -o test.net I get
unnamed_net3 R34-2 4-1 unnamed_net2 1-1 2-1 unnamed_net1 R34-1 3-1
On Thu, 2006-07-20 at 17:28 +0200, Arvid RosÃn wrote:
Stuart Brorson wrote:
I guess I don't see how shorting around a circuit involves connectingOk, I attached two sch-files which I think illustrates the problem quite well.
two nets which don't connect to anything else. Can you post a
simplified version of what you are trying to do? We can look at it
during the code sprint.
I tried this with the gnet-geda backend, and it fails discover that Rtop1 and Rtop2 should be connected.
Meanwhile, why not stick a zero ohm resistor into the shorting net,Yeah, sure. This is no problem as long as you are aware of it. But I just spent one day looking for errors in my netlister-backend.
similar to what John suggests? That way gnetlist has a component
which will preserve the net.
Stuart
I still think this is a strange behavior.
/Arvid
Stuart Brorson wrote:_______________________________________________
Just out of curiosity, why would you want to have two nets which connect to nothing other than each other?
Before we label it a bug, what is the goal of this construct? =20
Stuart
=20
Hi Stuart! That's a good question. The construct itself is quite pointless.=20 However, I was working on a quite complex design with two=20 filter-subcircuits. I wanted to test some aspects of my circuit, so I=20 shorted the first filter just to bypass it, which resulted in an open=20 circuit instead of a bypass! That is quite annoying, don't you think? The possibility to bypassing stuff is always important when debugging.
Cheers
Arvid
=2020
John Luciani wrote:
=20
On 7/20/06, Arvid Ros=3DE9n <arvid@xxxxxxxxxx> wrote:Ok, thanks!
=20
However, I also tried to make a 2-pin subnet containing only a short-circuit. This connection was completely ignored by gnetlist!!
Could someone confirm this?
=20
You are correct. If you have two nets that only connect to each other the connection does not show up in the netlist.
I get around this by connecting one of the nets to a component.
(* jcl *)
=20
Shouldn't that be considered as a pretty severe bug? I am new here,=3D=
_______________________________________________maybe it's already reported.
/Arvid
--=3D20 Arvid Ros=3DE9n Softube AB Teknikringen 7 S-583 30 Link=3DF6ping Sweden Phone: (+46) 13 21 16 23 Mobile: (+46) 73 25 12 34 7 Mail: arvid@xxxxxxxxxx URL: www.softube.se
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=20
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=20
--=20 Arvid Ros=E9n Softube AB Teknikringen 7 S-583 30 Link=F6ping Sweden Phone: (+46) 13 21 16 23 Mobile: (+46) 73 25 12 34 7 Mail: arvid@xxxxxxxxxx URL: www.softube.se
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plain text document attachment (test.sch) v 20060123 1 C 1000 4500 1 0 0 in-1.sym { T 1000 4800 5 10 1 1 0 0 1 refdes=3 } C 4600 6100 1 180 0 in-1.sym { T 4600 5800 5 10 1 1 180 0 1 refdes=2 } C 1000 5900 1 0 0 in-1.sym { T 1000 6200 5 10 1 1 0 0 1 refdes=1 } N 1600 6000 4000 6000 4 C 4600 4700 1 180 0 in-1.sym { T 4600 4400 5 10 1 1 180 0 1 refdes=4 } C 2300 4500 1 0 0 resistor-1.sym { T 2500 5000 5 10 1 1 0 0 1 refdes=R34 T 2500 4800 5 10 1 1 0 0 1 value=10k } N 2300 4600 1600 4600 4 N 3200 4600 4000 4600 4 plain text document attachment (top.sch) v 20060123 1 N 5000 9500 4300 9500 4 C 5000 9200 1 0 0 test.sym { T 5400 10300 5 10 1 1 0 0 1 refdes=Utest T 5400 9200 5 10 1 1 0 0 1 device=test T 5000 9200 5 10 1 0 0 0 1 source=test.sch } C 1700 8200 1 0 0 vac-1.sym { T 2400 8850 5 10 1 1 0 0 1 refdes=Vin T 2400 8650 5 10 1 1 0 0 1 value=dc 0 ac 1 } C 3400 9900 1 0 0 resistor-1.sym { T 3600 10400 5 10 1 1 0 0 1 refdes=Rtop1 T 3600 10200 5 10 1 1 0 0 1 value=10k } C 1900 7300 1 0 0 gnd-1.sym N 2000 8200 2000 7600 4 N 2000 9400 2000 10000 4 N 6800 9500 7600 9500 4 N 7600 10000 6800 10000 4 N 2000 8000 9000 8000 4 N 9000 9100 9000 10000 4 N 3400 10000 2000 10000 4 N 4300 10000 5000 10000 4 C 4300 9600 1 180 0 resistor-1.sym { T 4100 9100 5 10 1 1 180 0 1 refdes=Rtop3 T 4100 9300 5 10 1 1 180 0 1 value=10k } N 3400 9500 3000 9500 4 N 3000 9500 3000 10000 4 C 7600 9900 1 0 0 resistor-1.sym { T 7800 10400 5 10 1 1 0 0 1 refdes=Rtop2 T 7800 10200 5 10 1 1 0 0 1 value=10k } C 8500 9600 1 180 0 resistor-1.sym { T 8300 9100 5 10 1 1 180 0 1 refdes=Rtop4 T 8300 9300 5 10 1 1 180 0 1 value=10k } N 9000 10000 8500 10000 4 N 8500 9500 9000 9500 4 C 8900 9100 1 270 0 resistor-1.sym { T 9400 8900 5 10 1 1 270 0 1 refdes=Rload T 9200 8900 5 10 1 1 270 0 1 value=10k } N 9000 8200 9000 8000 4
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v 20060123 1
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