gEDA-user: Re: Icarus Verilog with Xilinx simprims...

[Stephen Williams <steve@xxxxxxxxxx>]

CSB wrote:
> First, I generate the post-fit verilog module from Xilinx ISE
> project navigator. This is the .v file containing all the nets
> and gates, for example X_AND2, etc... If I'm correct, those are
> defined in the *.v files of the XILINX/verilog/src/simprims/
> directory, one file for each module. They all contain timing
> information, which is what I'm after. So, I add
> "-y%XILINX%/verilog/src/simprims/" to my iverilog command,
> and it generates no error. Then, I run vvp, and generate a VCD
> from my testbench. So far, so good.

You'll get a logical simulation out of the post-route Verilog,
and that is somewhat valuable, but Icarus Verilog doesn't (yet)
support SDF back annotation of timing.

The latest Icarus Verilog snapshots *do* support some delay paths
types in specify blocks, but that won't help you much if you
really want the timings from back-annotation.

In practice, I and my day job colleagues do Xilinx designs and
don't miss the absence of back-annotation. If you do good functional
simulations before synthesis (and post par as well) and your
timing constraints are simple, then timing simulations are not
really needed. You only really want to do timing simulations if
you have complicated timing constraints that you specifically
want to test against a timing aware model of your external devices.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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