Re: gEDA-user: Hiding power pins in schematic symbols?

[Dave N6NZ <n6nz@xxxxxxxx>]

Frank Miles wrote:
> Newbie questioner...
> 
> Is there a way to selectively hide the power pins of a multi-sectioned component?
> That is, without having to resort to the "hidden connection" (net attribute) method?
Create multiple symbols.

> 
> A simple example: a 7400 package, with 4 2-in nand gates. 

I would create three symbols for this:
a) True-logic two input nand, with four slots.
b) Inverted-logic two input nor, with four slots (I can't help it, I 
spent too many years doing ECL... bubbles gotta match the signal 
polarity and function if you expect to survive a design review with me. 
A bubble/polarity mismatch indicates logical inversion.  And get off my 
lawn :)
c) A power symbol.

It's OK to have the same refdes assigned to multiple symbols, refdes and 
the 'slot' attribute is how the netlister sorts it all out.

I like to keep the logic on a logic page, and do one of two things with 
the power symbol.  On small designs, it goes in an out-of-the way corner 
of the same page as the logic symbols.  On large designs, all the power 
symbols go on a (some) page(s) designated as a "power symbol ghetto".

I used to use the hidden power attributes in order to reduce clutter, 
but in the end it creates more hassles than it solves.

-dave




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