gEDA-user: PCB design rule checker problems

[David Kuehling <dvdkhlng@xxxxxx>]

Hi,

I'm currently in the process of updating a design created quite some
time ago.  If I take the original design, the DRC now finds errors,
where it didn't find any in the old version.

I think I created the design with pcb-20060822.  Now I'm using
20070208p1 that comes with Ubuntu 7.10.

Errors seem to be related to pins and pads being located within the
convex hull of concave polygons.  Maybe the DRC isn't processing concave
polygons correctly?  Are concave polygons actually supported?

The other error is something I haven't seen before: a too thin silk line
(maybe this wasn't checked in previos versions?).  This is a real error,
the culprit being m4 macro COMMON_SMT_2PAD_MIL, which scales silk width
linearly with the size of the part [define(`silkW', `ifelse(eval(sizY >=
50), 1, 10, eval(sizY/5))')].

Any tips on how to get around these errors?  Do I need to update?  The
COMMON_SMT_2PAD_MIL-generated footprint looks like it needs to be
manually fixed (maybe a good opportunity to try out file elements...).

cheers,

David
-- 
GnuPG public key: http://user.cs.tu-berlin.de/~dvdkhlng/dk.gpg
Fingerprint: B17A DC95 D293 657B 4205  D016 7DEF 5323 C174 7D40



_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user