Re: [f-cpu] Supported Instructions

[Yann Guidon <whygee@f-cpu.org>]

hi,

nico wrote:
> Yann Guidon a écrit :
> > nico wrote:
<snip>
> > > - "something" (a register?) point on the faulty instruction.
> > in the CMB (the instruction pointer).
> > After the instruction is "simulated", the IP must be incremented...
> >
> > > - The handler try to extract the register number to emulate the instruction
> > use the IP from the CMB, fetch the 4-byte data and extract the fields.
> 
> So the hardware extract such fields ?
?
the emulation must be done in SW, so a few shifts and masks
do the job. I wonder why you imagined.

> Other wise it will be a true overkill !
draw your own conclusion

> > >  - by using some others registers ?
> > these are in the new "task". SRB is certainly triggered.
> >
> > >  - We need to save some of them (slow?)
> > why "slow" ?
> 
> If there is a context switch !

remember, at a time when the 80287 was overpriced...
people lived with that : SW emulation, libraries or coprocessor.
and they survived. If you use a FPU-less core, then you usually
take care to not use floats, and if it's FPU-intensive, then the
handler is in the cache. and if it's really FPU intensive and
your application is customized for you fpu-less core, then you compile
the code with emulation code : it will remove the traps, perform
the operations in integer world and the register allocation will be
much better.

you don't have anything for nothing.

> > >  - How to access indirectly the register set ? (to extract data)
> > fetch them from the CMB.
>
> So you must manipulate the instruction world and then manipulate the
> CMB. But it will be really slow !! Is it usefull ?

FP itself is at maybe 10x faster than emulated instructions, and FP is
pipelinable. so if you don't have a FPU, it's _necessarily_ slow.
come on.

You know that i refuse to design "naughty hacks" that will not be useful
(or that will harm us) in future architectures. You can maybe find an
idea but keep in mind that it must be compatible with all known
architecture and execution schemes. Triggering the SRB to get the
register set's image and instruction pointer is a simple and portable
way to perform the task. If you want to speed it up too much, you
will make the architecture and programming model too complex and
not implementable. And don't forget your P&H books :-) (you know,
"what is the definition of RISC"...)

Do you have an idea ?

WHYGEE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/