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[f-cpu] Erin64

    Good morning from the Gulf of Mexico.  A little History in the event it isn't taught anymore.
    The reason processors currently have a lot of Hardware Registers dates back to the early 1960's.  Core Memory was slow (1.0 micro second), so most companys used hardware to speed things up a bit.  Virtually all companys of the time did this except for ONE.  Honeywell Information Systems and that was the DDP-516.  I am emulating that Instruction Set Architecture (ISA) in my design of the Erin64 which has a single Register that is used as an Accumulator.  All other registers are assigned with a Symbolic Assembler - the number is limited by the size of Operand memory which is in my application a SSRAM having an access time of 4.5 Nano seconds organized 64 by 256K.
    I am also going to capture what was a working Language written in assembler code (9967 Instructions).  During the re-work process  we will further hand optimize the resulting assembled code and taylor it to the resulting hardware. 
    I will end with a distributed processing system (Not overly distributed) having a Language Processor, a Peripheral Processor, and up to 8 Math Co-processors serving up to 128 Users (CRT Monitors).  There is provision for "N" sub-systems beyond 128 Users.  All being serviced from a single Hard Drive Disk of 80 GBytes. I have not directed the Processor design to a "one size fits all" as you people are doing.  I am not competing with Intel and AMD as you people are doing.  I am certain they will come up with more answers while you are still in the "talking phase."  They do have a very large staff of hardware types and software as well.  However; I am not knocking your effort, it is very good education AND I WISH YOU VERY GOOD LUCK IN YOUR EFFORT.
    Richard E. Hartney
    Research Director
    Erin Greene & Associates