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Re: Rep:Re: [f-cpu] F-CPU vs. Itanium


Nicolas Boulay wrote:
-----Message d'origine-----
De: Martin Devera <devik@cdi.cz>
A: f-cpu@seul.org
Date: 22/04/02
Objet: Re: [f-cpu] F-CPU vs. Itanium

It makes the same problem as a plain C simulator : we already have to
deal with
a VHDL source tree and there are too few contributors yet. we can't
anybody, you know : it's all volunteer work. when work is done.

true .. The biggest problem I see: is there any free tool to use
for simulation cpu (or other logic) in VHDL ? If not it too hard
to write one ?
I ask because when I developed first version of advanced packet
I did it in userspace - I was able to quickly evaluate speed and has
forced to rethink/rewrite whole agorithm three times (the complexity
analyse is almost impossible there) - it saved a lot of time - then
I implemented it once in kernel space (which is a bit harder/slower).
I was thinking about emulator where all ideas can be quickly evaluated
million times before you start coding actual logic.
And if there would be single tool used by all participants I think that
some ideas could be tested very fast.

That's where goes the big design. They called that architecture
exploration. Industry try to introduice many tools to create a flow from
the spec to the GDS II files.
System C are design to do such research. The idea is to "refine" your
design with VHDL like concept. BUT you could begin dirty C++ if you
want. That's where you could save time.

slow if we can't access full-custom technologies (like Intel and IBM
Beyond, another strategy must be used.

I'm not experianced here, what is difference between ASIC and full
custom ? ASIC can use only predefined blocks ?
A full-custom is generally implemented into an ASIC, but an ASIC can be not a full-custom.

The ASIC term cover some other concepts. The main point to remember  is than ASIC is a specific-application oriented design chip. In example, you couldn't implement into a FPGA a asynchronous design (because the FPGA have a main synchronous clock input, which drive all internal sequential cells), to do it you need an ASIC (because you implement as much clock as you like to drive the sequential cells). The cpu can be generally attach to the ASIC familly.

ASIC are a generic name. Most (99%) of the design use semi-custom
design. In fact, the design is an interconnection of soon defined cells
(AND/OR gate, register,...). Most of the time they define memory bloc,
too. But this kind of block have 2 ports, very few times more.

So you need full custom design where you could design you're one
memory block. But it's far more expensive for a compagny to do it. Most
of the time only foundries do it (IBM, ST, TSMC,...).

The third kind of ASIC called 'precaractérisé' in french are a kind
of FPGA, only the 2 or 4 last metal layer are define by the designer.
That's the chipest technology.

university did it but they have working 3 ported 32x31 register set
operating at 16GHz with only 20W of thermal loss.
"only" ?...

hmm not too low abs. number ;) But they computed 16GHz in cmos would
much more .. Also they claim that with higher integration this number
will decrease and in cmos it increases ..

??? 20 W for a register bank is hudge ! In 400 Mhz only 7W is needed
for the whole mutiplier unit (0.18 µm).


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