Re: [f-cpu] IDU News; synthesis report

[devik <devik@cdi.cz>]

> > > > By the way, I synthetized scalar 64 bit adder and 32bit multiplier
> > > > for compare.
> > > > Adder (not pipelined): 120 MHz, 155 slices
> > > > Adder (2 stages):      160 MHz, 198 slices
> > >
> > > That's a plain adder, right?  No subtract, saturate or average
> > > functions?
> >
> > exactly. It is ripple carry adder. I did pipelined one by
> > splitting it into 2 32 bit parts.
> > XST detects "+" operators and uses internal fast-carry
> > chain. It needs only 50 ps (picoseconds) per carry.
>
> Can you try a simple carry-select adder?  I'll attach a copy.

Ok, 310 slices, 65 MHz on Spartan2E. Seems ripple one
is superior on fpga because they have dedicated circuits
for it. Maybe one could create 8 8bit ripple adders
and add carries in next stage - these +1 adders could
use fast carry chain again ...

devik

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